The present invention relates to a xcfx80/4 shift QPSK modulator, as well as a communication device, which is suitable for use of ICs in communications using digital signals.
Conventionally, as a digital signal modulation system, the QPSK (Quadrature Phase Shift Keying) system has been widely used. In this QPSK system, a filter having roll-off characteristics is used as a band-limiting filter so that intersymbol interference is eliminated. This filter having roll-off characteristics is, in many cases, a digital filter because of complex characteristics. However, in this digital filter, since arithmetic processing of signals is executed by multiplications and additions, the arithmetic processing needs to be executed at high speed.
Thus, in order to keep up with this higher-speed arithmetic processing, there has been proposed a technique that the digital filter is replaced with ROM by previously storing processing results in ROM (Read Only Memory) and by feeding input data as ROM addresses (see Japanese Patent Laid-Open Publication SHO 53-24763).
There has also been proposed a symbol tap ROM division method that the digital-filter ROM is divided in every accumulative symbol tap (xe2x80x9cxcfx80/4 QPSK Baseband Signal Generator Using Symbol Tap Divided ROMxe2x80x9d, Proceedings of the 1992 Spring Conference of IEICE (Institute of Electronics, Information and Communication Engineers)). The digital filter of this xcfx80/4 QPSK baseband signal generator using the symbol tap divided ROM, as shown in FIG. 6, comprises: nine unit delay circuits 61 for delaying 2-bit symbol mapping data in symbol cycles; totally nine ROMs 62 to which an address is given by totally 6 bits composed of 2-bit for output of each unit delay circuit 61 and 4-bit for time information; an adder 63 for adding up output data of the ROMs 62; and a D/A (digital-to-analog) converter 64 for converting output data of the adder 63 into analog form. The ROMs 62 are driven by a clock sixteen times higher than the symbol clock (oversampling). Data lengths of the nine ROMs 62 of the digital filter are 4, 5, 7, 10, 11, 10, 7, 5 and 4 bits, respectively, by simulating dynamic ranges of impulse response of the root Nyquist filter in every symbol interval.
Like this, by determining data lengths corresponding to necessary dynamic ranges in every symbol interval, the total capacity of the ROMs 62 is reduced without lowering the processing precision. Also, by time-dividing I and Q phases of the symbol mapping data, a xcfx80/4 shift QPSK baseband signal generator is implemented with one digital filter.
Further, a xcfx80/4 shift QPSK modulator in which circuit scale and ROM capacity are kept low is disclosed in Japanese Patent Laid-Open Publication HEI 3-235553. There has also been disclosed, in Japanese Patent Laid-Open Publication HEI 7-50693, a technique that in the xcfx80/4 shift QPSK modulator, ROM capacity is reduced by commonizing the phase information I, Q to the ROMs.
FIG. 5 is a main-part block diagram of the ROM capacity reducing technique by using a ROM in common to phase information I, Q, as described in Japanese Patent Laid-Open Publication HEI 7-50693. In FIG. 5 are shown a mapping circuit 50, an oversampling counter 51, an impulse response computing circuit 52, cumulating circuits 551, 552, and D/A converters 571, 572. The impulse response computing circuit 52 has therein a ROM 54 in which impulse response data of two kinds of phase information are stored, sign inverting circuits 526, 526 for performing sign inversion of impulse response data derived from the ROM 54, and zero output circuits 527, 527 for replacing outputs of the sign inverting circuits 526, 526 with zeroes. Since the ROM 54 is provided in common to two systems of phase information (I and Q components) perpendicular to each other, only one ROM 54 will do for phase information (I and Q components) and the storage capacity of the ROM 54 can be reduced.
Further, it is conceivable to make up a xcfx80/4 shift QPSK modulator shown in FIG. 4 by combining the prior arts of FIG. 5 and FIG. 6 as described above.
As shown in FIG. 4, a signal representing phase information outputted from a mapping circuit 10 is inputted to impulse response computing means 42. The inputted data is shifted with a shift register 421 by a symbol clock 13. Then, as shown in a signal arrangement view of FIG. 2, signal modulation is done by shifting a reference phase by xcfx80/4 in every symbol cycle. Referring to FIG. 2, a signal of a point xe2x80xa2 is transmitted at an even-numbered timing, and a signal of a point o is transmitted at an odd-numbered timing. That is, a phase state xe2x80x9coxe2x80x9d becomes a phase state xe2x80x9cxe2x80xa2xe2x80x9d with a shift of xcfx80/4 at the next symbol timing. Also, after phase information is differentially coded at each xe2x80xa2 and o, the phase information is divided into vectors of I component and Q component at the individual points xe2x80xa2 and o, and based on these pieces of information, mapped into magnitude information, sign information and zero replacement information by the mapping circuit 10. Then, symbol mapping data from the mapping circuit 10 is inputted to the shift register 421 (7 taps), and a total sum of impulse response values corresponding to signals representing the phase information time-delayed by the shift register 421 is computed, by which filter characteristics are fulfilled. Further, outputs from the registers D1-D7 of the shift register 421 are inputted to impulse response storage sections 424 (ROM1-ROM7), respectively, in which impulse response data have been dividedly stored. In these impulse response storage sections 424, an impulse response waveform (shown in the schematic view of FIG. 4) is divided into 7 symbol intervals, and impulse response data corresponding to a magnitude xcex1 and a magnitude xcex2 are oversampled in each symbol interval and stored into the ROM1-ROM7. Output values from an oversampling counter 11 of FIG. 4 correspond to sample numbers of FIG. 3, and impulse response data corresponding to the sample numbers are stored in the impulse response storage sections 424.
FIG. 3 shows impulse response data (amplitude values of impulse response waveform) stored in a ROM2 of the xcfx80/4 shift QPSK modulator shown in FIG. 4. Referring to FIG. 3, according to the sample numbers 1-16 and the magnitude information derived from the registers D1-D7 of the shift register 421, impulse response data is read from the ROM2, and the impulse response data read from the ROM2 is inputted to a numerical value conversion section 426 corresponding to the ROM2. Also, sign information and zero-replacement information contained in a signal representing phase information derived from the shift register 421 are time-divided by an IQ time-division clock 14 by a selector 425 and inputted to the numerical value conversion section 426. This numerical value conversion section 426 executes, as appropriate, sign inversion or zero replacement for each of phase information I and phase information Q with respect to the impulse response data derived from the ROM2. Then, outputs from all the numerical value conversion sections 426 are added up by an adder 15, separated into I component and Q component by latch circuits 161, 162, and the separated I component and Q component are converted into analog form by D/A converters 171, 172. Thus, modulation signals of I output and Q output are produced, respectively.
In the xcfx80/4 shift QPSK modulator shown in FIG. 4, which is based on a system that the principle of convoluting operation is applied to ROM filter implementation, a ROM data map is provided by partitioning a single-pulse root Nyquist filter pass waveform in every symbol interval, and by sampling the partitioned waveforms at an appropriate oversampling frequency, thus giving rise to a need for two kinds of magnitudes of impulse response data for the phase information of symbol intervals. As shown in FIG. 3, since a single-pulse root Nyquist filter pass waveform is bilaterally symmetrical with respect to a peak value, ROM data can be compressed to xc2xd by virtue of this characteristic.
However, in this xcfx80/4 shift QPSK modulator, only by cutting down the root Nyquist filter pass waveform to a one-side half, two phase-information read address signals would make access to the ROMs simultaneously, necessitating such a countermeasure as doubling the reading rate from the ROMs, which would cause disadvantages in terms of power consumption and the like. There is a further problem, in addition to such problems, that the circuit would be complicated due to the concurrent timing for read address signal switching and convoluting operations.
Therefore, an object of the present invention is to provide a xcfx80/4 shift QPSK modulator, as well as a communication device, which is capable of reducing the storage capacity of ROMs for previously storing impulse response data, and which allows power consumption to bexe2x80x94lowered and circuit scale to be downsized.
In order to achieve the above object, the present invention provides a xcfx80/4 shift QPSK modulator comprising: phase information computing means for computing a QPSK modulation signal according to an input signal, and outputting a signal representing phase information of the modulation signal; impulse response computing means for computing and outputting impulse response data corresponding to a signal representing the phase information derived from the phase information computing means; and impulse response cumulating means for cumulating the impulse response data derived from the impulse response computing means, and outputting the modulation signal based on a result of the cumulation, wherein the impulse response computing means comprises: shift registers of an even number of stages for delaying signals representing the phase information derived from the phase information computing means one after another in every symbol cycle; a plurality of impulse response storage sections for previously storing the rein divided impulse response data in every symbol interval, the divided impulse response data being obtained through steps of determining impulse response data by oversampling a one-side waveform of a bilaterally symmetrical impulse response waveform corresponding to a magnitude xe2x80x9c1xe2x80x9d of I component and Q component of the phase information, and a one-side waveform of a bilaterally symmetrical impulse response waveform corresponding to a magnitude xe2x80x9c1/{square root over (2)}xe2x80x9d of I component and Q component of a signal representing the phase information, respectively, based on a clock having a cycle which is a multiple of the symbol cycle, and dividing the individual impulse response data in to symbol intervals which counts a half of the number of stages of the shift registers; a read address control section for outputting a read address signal to each of the impulse response storage sections so that for a symbol interval of impulse response data that has been stored in the impulse response storage sections, impulse response data of the symbol interval is read out in a forward direction, while for a symbol interval of impulse response data that has not been stored in the impulse response storage sections, impulse response data of a symbol interval that is bilaterally symmetrical with the symbol interval is read out in a reverse order, based on the magnitude xe2x80x9c1xe2x80x9d or xe2x80x9c1/{square root over (2)}xe2x80x9d of I component and Q component of signals representing phase information of the stages delayed by the shift registers; and a numerical value conversion section for performing sign inversion and zero replacement of impulse response data read out from the impulse response storage sections according to signals representing phase information of the stages delayed by the shift registers.
According to the xcfx80/4 shift QPSK modulator of the present invention, the phase information computing means computes a QPSK modulation signal according to an input signal, and outputs a signal representing phase information of the modulation signal, and the shift registers of an even number of stages of the impulse response computing means delay signals representing the phase information one after another in every symbol cycle. Based on the magnitude xe2x80x9c1xe2x80x9d or xe2x80x9c1/{square root over (2)}xe2x80x9d of I component and Q component of signals representing phase information of the stages delayed by the shift registers, the read address control section outputs a read address signal to each of the impulse response storage sections so that for a symbol interval of impulse response data that has been stored in the impulse response storage sections, impulse response data of the symbol interval is read out in a forward direction, while for a symbol interval of impulse response data that has not been stored in the impulse response storage sections, impulse response data of a symbol interval that is bilaterally symmetrical with the symbol interval is read out in a reverse order. Then, the impulse response storage sections each output impulse response data that have been divided in every symbol interval, which count a half of the number of stages of the shift registers, and that have been previously stored, in correspondence to the magnitudes xe2x80x9c1xe2x80x9d and xe2x80x9c1/{square root over (2)}xe2x80x9d of I component and Q component of the phase information. The impulse response data read out from the impulse response storage sections are subjected to sign inversion and zero replacement processes by the numerical value conversion section according to signals representing phase information of the stages delayed by the shift registers. Then, the impulse response cumulating means cumulates the impulse response data derived from the impulse response computing means, and outputs the modulation signal based on a result of the cumulation.
Like this, in the impulse response storage sections of the impulse response computing means, impulse response data obtained by oversampling a one-side waveform of an impulse response waveform (a single-pulse root Nyquist filter pass waveform) bilaterally symmetrical with respect to a peak value is used in common according to a symbol tap ROM division method, which is a method for dividing ROM of a digital filter in every symbol interval. By making the data length of the commonized data in the impulse response storage section per symbol interval into a data length equivalent to a dynamic range necessary for each symbol interval, the storage capacity of the impulse response storage sections can be reduced. Also, the read address control section of a simple construction switches a read address signal so that the impulse response storage sections which have stored impulse response data corresponding to the two kinds of magnitudes xe2x80x9c1xe2x80x9d and xe2x80x9c1/{square root over (2)}xe2x80x9d in every commonized symbol interval are not accessed simultaneously. Therefore, the storage capacity of the impulse response storage sections for previously storing impulse response data therein can be reduced, and power consumption can be lowered and the circuit scale can be lessened.
Also, in an embodiment, the numerical value conversion section comprises: a zero replacement section for performing zero replacement of impulse response data corresponding to the magnitude xe2x80x9c1xe2x80x9d of I component and Q component of signals representing phase information of the stages delayed by the shift registers out of the impulse response data read out from the impulse response storage sections, based on a signal representing the phase information; and a sign inversion section for performing sign inversion of impulse response data corresponding to the magnitude xe2x80x9c1/{square root over (2)}xe2x80x9d of I component and Q component of signals representing phase information of the stages delayed by the shift registers out of the impulse response data read out from the impulse response storage sections, based on a signal representing the phase information.
According to the xcfx80/4 shift QPSK modulator of this embodiment, a signal representing the phase information contains not only I component and Q component magnitude information but also I component sign inversion information, I component zero-replacement information, Q component sign inversion information and Q component zero-replacement information. The zero replacement section of the numerical value conversion section performs zero replacement, when the zero replacement is necessary, based on the I component and Q component zero-replacement information contained in the signal representing the phase information, on impulse response data corresponding to the magnitude information xe2x80x9c1xe2x80x9d in I component and Q component of signals representing phase information of the stages delayed by the shift registers out of impulse response data read out from the impulse response storage sections. Also, the sign inversion section of the numerical value conversion section performs sign inversion, when sign inversion is necessary, based on I component and Q component sign inversion information contained in a signal representing the phase information, on impulse response data corresponding to the magnitude information xe2x80x9c1/{square root over (2)}xe2x80x9d in I component and Q component of signals representing phase information of the stages delayed by the shift registers, out of the impulse response data read from the impulse response storage sections. Therefore, sign inversion and zero replacement processes corresponding to two pieces of phase information derived from the shift registers can be implemented by one numerical value conversion section, so that the circuit scale can be further reduced.
In an embodiment, a communication device uses the above xcfx80/4 shift QPSK modulator.
According to the communication device of this embodiment, the storage capacity of ROM for previously storing impulse response data of the xcfx80/4 shift QPSK modulator can be reduced, and besides power consumption as well as circuit scale of the xcfx80/4 shift QPSK modulator can be reduced. Therefore, a communication device of smaller size and lower power consumption can be realized.
In an embodiment, a communication device uses the above xcfx80/4 shift QPSK modulator for a PHS (Personal Handy-phone System).
According to this embodiment, the storage capacity of ROM for previously storing impulse response data of the xcfx80/4 shift QPSK modulator can be reduced, and besides power consumption and circuit scale of the xcfx80/4 shift QPSK modulator can be lowered. Therefore, a communication device of further smaller size can be provided for PHSxe2x80x2 which are in demands for smaller size, lighter weight and lower power consumption.